Camera module driver OV7725
August 7, 2021
Camera driver OV7725 electrical characteristics and timing diagram
The information about OVsensor includes, OV7725 introduction (OmniVsion_OV7725), OV7725 data manual (OV7725_Datasheet), OV7725 SCCB interface timing (OmniVision Serial Camera Control Bus (SCCB)
Functional Specification), OV7725 Register Configuration Manual (OV7725 Camera Module Software Application Note).
A camera is as follows:
OV7725 hardware circuit
The above picture is the drive circuit of OV7725. Note that sclk and sdat should be connected to 4.7K pull-up resistors. This is because the SCCB interface is essentially an I2C interface, and its output terminal is open-drain or open-collector, and it can only output low level. , So pull-up resistors must be connected at the two interfaces. Pay attention to this, otherwise it will cause unsuccessful communication.
The I2C interface recognizes and accesses through the unique address of the slave, which can realize the control of each device. This transmission method can reach 100kbps in standard mode, 400 kbps in fast mode, and 3.4Mbps in high speed.
Figure 1 is mainly the internal structure of the OV7725, which is mainly driven by the XCLK clock to sample image data. SCL and SDA are the interfaces of SCCB, and the other interfaces are the signals output by OV, including HREF, PCLK, VSYNC, and the data output interface, a total of 10 bits. Note that in the DSP module, lens shading correction, noise reduction, white/black pixel correction, automatic white balance, etc. can be realize.
Regarding the zoom function, which can be zoomed from VGA mode to CIF mode, or even lower than CIF mode.
The picture above is the format that OV can output.
OV7725 can reach 60fps in VGA mode. You can use the SCCB interface, which is actually similar to the I2C interface, for white balance, gama, color correction, exposure control, tone control, etc. Figure 1 can also see the relevant architecture.
The picture above is the pin diagram of OV7725. The pins used are shown in the figure below:
It can also be seen from the above figure that for RAW RGB data output 10bit, if the output for other formats is 8bit, take the higher 8bit of D output.
The above figure shows the electrical characteristics of OV. The typical value of the analog power supply is 3.3V, the typical value of the digital voltage is 1.8V, and the IO interface voltage can be 3.3V.
In the above figure, the drive clock requires 24MHz, and the SCCB interface clock is up to 400KHz. It should also be noted that for each register change, a maximum delay of 300ms is required, which is 10 frames.
The above figure is the timing diagram of the SCCB interface, and also the timing diagram for realizing various register configurations. The clock requirement of SCL cannot exceed 400KHz.
Mosaic diagram of output in RGB565 format.
Mosaic diagram of output in RGB555 format.
The figure above realizes the output data with the PCLK clock frequency when HREF is valid. And realize the splicing of data. The above figure is a schematic diagram corresponding to data splicing, which realizes RGB565/RGB555/RGB transmission.
Mosaic diagram of output in RGB444 format.
Timing diagrams of different frame formats
Note that the output clock of PCLK when outputting a frame of image mentioned above is mentioned in the OV7725 Register Configuration Manual (OV7725 Camera Module Software Application Note), as shown in the following figure: