Realization of camera driver 0V7725 SCCB timing
September 3, 2021
Realization of camera driver 0V7725 SCCB timing
SCCB interface timing
The start and stop signals of the dual bus are shown in the figure below. Among them, SCCB_E is an enable signal set for multiple slave devices. Here, only one sensor is used for data configuration. So this signal can not be used.
The above is about the start and stop signal timing diagram.
The above figure shows the relevant settings for writing to the register. Set the ID address first, then write the register address, and finally write the value of the register.
The first stage: For OV, the device address is 0X42, writing is 0X42, and reading is 0X43;
The second stage: write register address, this address is the address value of OV you need to set;
The third stage: the value written into the register, which corresponds to the address value of the register set in the second stage;
For reading the register, the manual has such a paragraph description.
Therefore, for the read phase in the above figure, we intend to use four phases to achieve, one is to use the same first two phases as the write register, including the ID address and the register address to be set, and then add two phases, one It is to read in the ID address again, and then read out the data value. As shown below:
For the OV register, some register values are suitable for reading, and some register values are suitable for writing. Therefore, pay special attention to the format configuration of various data when setting the OV register. The following is the implementation of the I2C interface and the register configuration of the OV7725.
The above figure is the overall block diagram of the SCCB interface, which does not draw the global clock and global reset signal, and the global clock and global reset control are required when redesigning.
The implementation code is as follows:
I2C_OV7725 configuration module
The above figure is a brief list of the parameter settings. Note that the register 12 and 37 lines are for resetting, and the 64 line is for setting the output form.
It is stipulated in the manual that after all registers are reset, a delay of no more than 1ms is required to ensure stability to the greatest extent.
The figure above is the port declaration and the 1ms power-on delay to complete.
The above is to complete the generation of SCL and set the enable signal in the middle of the clock. The simulation diagram is shown in the figure below:
The various states of the state machine.
The figure above is the first part of the state machine. As mentioned in the manual, if a register is not changed, a maximum delay of 300ms is required. The minimum and typical values are not specified, as long as it is less than or equal to 300ms. Use i2c_transfer_end and i2c_ack to achieve this delay. Among them, i2c_ack is the total response of each stage. It will be mentioned below.
The figure above is the first part of the state machine. As mentioned in the manual, if a register is not changed, a maximum delay of 300ms is required. The minimum and typical values are not specified, as long as it is less than or equal to 300ms. Use i2c_transfer_end and i2c_ack to achieve this delay. Among them, i2c_ack is the total response of each stage. It will be mentioned below.
It should be noted in line 188 that the first two registers are used to generate the vendor ID and are read-only, so judgment is required.
In the above figure, i2c_stream_cnt is used to count data bits, so that when sending, it is sent from high to low.
In the above figure, i2c_sdat_out is used as the output data register to receive the data sent by the configuration register module.
The above picture is the response to the I2C ack signal, the response from lines 420 to 422 is high impedance state, and the following is the modelsim simulation diagram of the interface implemented by the entire SCCB.